Please see the complete documentaion for an explanation of the D Flip Flop.
The Q terminal and the Q╨not terminal output opposite digital levels (0.0 or 1.0). The Q terminal's output is determined by input to the module; and the Q╨not's output is determined by the Q's output. There is one exception to this noted in the section on the set and reset terminals.
The set terminal forces the Q output high when input to it goes high. The Q output stays high even after the set input goes low.
The reset terminal has the opposite function of the set terminal. When input to the reset terminal goes high, the Q output goes low and stays low until it is set high again by a high input to the set terminal.
If input to both the set and the reset terminals are high, both the Q and the Q╨not outputs are high at the same time.
The moment the clock terminal goes high, the input to the data terminal becomes the basis for the Q terminal's digital output.
